Integrated circuit (IC) memory devices store large amounts of data in relatively small physical packages. Exemplary IC memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), and read only memory (ROM), such as erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.
Typically, an IC memory device comprises a plurality of cells into and from which data can be transferred for storage and retrieval. During such transfers, various signals are used to convey data and to control and coordinate the storage/retrieval of the same. These transfers can be made using industry-wide standard protocols, such as the PC100 bus standard initiated by Intel Corp. to support next generation PC systems.
Various input/output (I/O) interfaces have been previously developed to enable such transfers of data to and from the cells of an IC memory device. The following is a listing of various IC memory devices which incorporate previously developed I/O interfaces:
1. Fast Page Mode (FPM) DRAM is a single bank architecture which supports bursts of data (FPM access) from a memory storage array with transistor-to-transistor logic (TTL) interface technology. Parameters for this interface are as follows: V.sub.IL =0.8V, V.sub.IH =2.4V; V.sub.OL =0.8V, V.sub.OH =2.4V. The I/O interface is asynchronous. PA1 2. Extended Data Out (EDO) DRAM extends single bank FPM architecture by adding a data validation window for faster timing with TTL or low-voltage TTL (LVTTL) interface technology. Parameters for LVTTL I/O interface are as follows: V.sub.IL =0.8V, V.sub.IH =2.0V; V.sub.OL =0.8V, V.sub.OH =2.0V. This interface is asynchronous. PA1 3. Synchronous DRAM (SDRAM) is a multi-bank architecture with an added free-running clock for simplified circuit design using TTL or LVTTL interface technology. This architecture allows bank interleaving to minimize row-address strobe (RAS) access time latency. The I/O interface of SDRAM is synchronous. PA1 4. Double Data Rate (DDR) SDRAM is an extension of SDRAM. In DDR SDRAM, data is transferred on both edges of a clock. A read strobe is provided for increased reliability. Control and address signaling is performed with LVTTL interface technology. Clock, data, and mask signaling is performed with stub series terminated logic (SSTL) interface technology. The parameters for SSTL technology are as follows: V.sub.DD =3 +/-0.3V; V.sub.REF =1.3V to 1.7V; V.sub.IL =V.sub.REF -0.2V, V.sub.IH =V.sub.REF +0.2V; V.sub.OL =V.sub.tt -0.8V, V.sub.OH =V.sub.tt +0.8V, V.sub.tt =V.sub.REF +/-0.05V. The maximum data rate is 250 Mbps/pin. PA1 5. Direct Rambus.TM. DRAM (Direct RDRAM.TM.) is similar to SDRAM, but replaces that architecture's I/O interface with a Rambus proprietary I/O interface technology. Direct RDRAM uses multiplexed row and column buses, and adds pipelined, packet-oriented transfer protocol I/O with Rambus Signaling Level (RSL) technology. The parameters for RSL technology are as follows: V.sub.DD =2.5V+/-5%; V.sub.REF =1.4+/-0.07V; V.sub.IL =V.sub.REF 0.5V; V.sub.IH =V.sub.REF +0.5V; V.sub.OL =1.0V; V.sub.OH =1.8V. The data rate is approximately 600-800 Mbps/pin. PA1 6. SyncLink.TM. DRAM (SLDRAM) utilizes pipelined, packet-oriented transfer protocol I/O with timing calibration (SyncLink proprietary) for increased DRAM bandwidth. The parameters for SLDRAM I/O (SLIO) interface technology as a follows: V.sub.DD =2.5V+/-5%; V.sub.REF =0.5 V.sub.DD +/-0.05V; V.sub.IL =V.sub.REF -0.2V, V.sub.IH =V.sub.REF +0.2V; V.sub.OL =0.9V; V.sub.OH =1.6V. The data rate is 400 Mbps/pin.
Each of the previously developed I/O interfaces listed above utilizes only two voltage levels for the information signals by which data is transferred to and from a memory device. Thus, with previous techniques, the only way to increase the transfer bandwidth of information (e.g., data or control) is to increase the speed or frequency at which a respective information signal is input or output. Because high frequency operation requires very dedicated small-signal handling and careful impedance match, the operational capability of previously developed I/O interfaces is limited.
As processors, controllers, and other devices which operate with IC memory are continuously improved, however, the rate at which data is desired increases. For example, central processing units (CPUS) operating at over 300 MHz and media processors executing more than two Giga Operations (GOPs) are now in production. Such processing devices require more than 500 Mbytes/s memory bandwidth. With the PC100 bus standard and state-of-the-art dynamic random access memory (DRAM) technology, DRAMs operating at 100 MHz are barely able to fulfill this bandwidth requirement. Furthermore, the projected memory bandwidth requirement for multimedia three-dimensional graphics applications exceeds 1 Gbytes/s. This transfer rate is well above what such IC memory devices can offer.
Furthermore, previously developed I/O interfaces require a separate pin connection for each signal used to transfer, or control the transfer of, information to and from an IC memory device. For example, each address signal, control signal, data signal, and the like, must be supported by its own pin connection in previously developed I/O interfaces. As the capacity and complexity of IC memory devices increases, the pin connections required to support signaling can become quite extensive. Numerous pin connections give rise to substantial electro-magnetic interference (EMI) on a PC board. Furthermore, a device with a large pin-count typically has a larger chip area and consumes more power.